1. Field of the Invention
This invention relates to methods and hardware apparatus for the counting and concatenation of one- or more-bit digital data segments into larger words for more efficient transmission and CPU utilization and related purposes.
2. Background of the Invention
Computer operations in general rest upon the premise that particular collections of data bits, when produced within a program or when entered by an operator, will bring about some desired result, as when a word corresponding to a word in some command set is produced within a program to cause a particular operation to take place, or when ASCII code is used to enter alphanumeric data into a program, likewise either to bring about some desired operation or simply for storage of such data, or indeed in the transmission of voice, imagery or video communications and the like. What may be termed the xe2x80x9csensexe2x80x9d of the word as a command mnemonic or some other meaning then requires some kind of byte-by-byte xe2x80x9cinterpretivexe2x80x9d process to be carried out by the CPU.
One disadvantage of such a byte-by-byte procedure is that it may utilize clock cycles within the CPU unnecessarily. A purpose in avoiding use of the CPU is that if one can accomplish a task using some fraction of the number of clock cycles that would otherwise be required, then the throughput of the CPU, with respect to that particular task, will be multiplied in a corresponding ratio. Similarly, if a communications pathway or bus is constructed so as to accommodate, say, 16-bit, 32-bit or larger words, but in each clock cycle is being used instead to convey 8-bit bytes, for those operations the CPU is correspondingly being underutilized by a factor of 2 or 4 or more, as the case may be.
Also, because of the well-known von Neumann bottleneck, operations requiring use of a CPU are likely to be carried out much slower than they might be otherwise, e.g., as in a gate array. In lieu of various concatenation and interpretive procedures that employ a CPU, it has thus seemed useful to provide a method and apparatus for carrying out such operations by hardware means that are separate from any CPU. The purposes in so doing include not only minimization of CPU usage, but also introduction of greater data transmission efficiencies and the avoidance of software errors, e.g., either fixed xe2x80x9cbugsxe2x80x9d or soft errors. The principle of the invention rests on the premise that greater efficiency in computer operations can be achieved by processes by which the data to be treated are xe2x80x9cconditionedxe2x80x9d prior to entry into the computer, by which is meant that they are so treated as to maximize both the efficiency of their transmission into the computer and the efficiency of their processing within the computer.
Such operations as concatenation, sorting, and other data manipulation have of course become routine as part of computer operations, and numerous programs have been written therefor but, no doubt because of the astounding success of such computer operations, there seems to have been developed very little in the way of asynchronous circuitry that would perform the same or similar tasks, and perhaps precisely because of the success of related computer-controlled operations. One kind of operation that would seem to lend itself to such treatment is that of serial-to-parallel (S/P) conversion, which is done conventionally by means of clock-operated shift registers that accumulate a sequence of n serial bits that are then read in parallel so as to effect the desired conversion.
One effort to avoid CPU use in the context of serial-to-parallel conversion is seen in U.S. Pat. No. 5,862,367 issued Jan. 19, 1999 to Chiao-Yen. This device acts in response to a chip select signal by separating certain pre-determined identifying information (that will specify a particular receiving register) from associated data portions of the received serial data and then transmitting the data portion when rendered parallel to the selected receiving register. S/P conversion is accomplished by an array of D-type flip-flops having common reset signals RS and clock signals CK so as to function as a shift register in the usual manner. The incoming data are thus both rendered parallel and placed into particular receiving registers, i.e., the data are sorted in accordance with pre-determined criteria so as to yield a collection of parallel words residing in pre-determined registers or memory locations.
Another, more complex S/P circuit is found in U.S. Pat. No. 4,079,373 issued Mar. 14, 1978 to Koenig. This device is specifically adapted to treat incoming data that, similar to those of the Chiao-Yen device, are separated into discrete data formats and control formats. Varying numbers of control bit sets are presumed to arrive at irregular times, and the last of such bit sets in a particular sequence signals that the set of data next to follow comprises data bits that are to be converted from serial to parallel form, for which conventional shift register means operated by a clock signal are used to accomplish the S/P conversion.
Both of the foregoing devices are limited in general applicability in that they assume a particular formatting or structure to be present in the incoming serial data, and require a clock signal since they use conventional flip-flop or TTL shift registers. The effect of using a clock signal is of course to fix the rate of S/P conversion, without regard to variations in the rate at which data may be received. In the case of data that are received by a modem or the like, such data reception rates may vary considerably in practice, depending upon such factors as the load currently being imposed on the originating data source and the intervening transmission means, hence it seemed useful to be able to adjust the rate of S/P (or any other kind of conversion) to the actual data reception rate, e.g., to permit the device to function asynchronously. The concomitant speed advantage of asynchronous logic circuits might then be xe2x80x9cweddedxe2x80x9d to various other advantages provided by computers, while at the same time avoiding use of the CPU, and thereby to enhance the operation of those computers themselves.
The invention accomplishes those purposes both as to S/P conversion and to what may be termed a xe2x80x9clarger word equivalentxe2x80x9d thereof, i.e., the concatenation of data sequences larger in number that the single bits treated in S/P conversion. Data paths to the CPU, whether from a modern or the like or from sources internal to the computer, can then be more fully exploited. The invention comprises both a data enumerator wherein a xe2x80x9csequence numberxe2x80x9d or xe2x80x9cposition numberxe2x80x9d is appended to each data segment as it is received, and a digital concatenator that then accepts such a series either of signals bits or bytes, as for example 8-bit ASCII characters, and concatenates those bits into bytes or words of selected length (i.e., standard S/P conversion), or concatenates such bytes into 16-, 24-, 32-bit or larger words while retaining the sequencing of those bytes within a larger word path or register. Separate instances of the concatenator can also be cascaded in pre-selected combinations to achieve any desired data format. If the incoming data sequences have a known structure, the computer can be programmed to handle them more efficiently in that such longer length words can be immediately disassembled to send the separate parts thereof into registers having known addresses for specific pre-determined purposes.